The state-of-the-art of VLSI integrated digital circuits is constantly being pushed in, among other characteristics, speed capabilities. The density of state-of-the-art VLSI has reached a development stage at which it is possible to implement entire multi-processor systems in a single, relatively small housing with several subsystems, such as individual central processors, input/output units, system control units, memories, etc. each contained,or mounted on a single printed circuit board. These subsystems exchange information on busses which are often implemented as numerous conductive traces on a backpanel into which the subsystem circuit boards are plugged. The several subsystems communicating among themselves, or with one another, along a given bus are sometimes called "transaction members".
As the speed capabilities of the circuitry contained in subsystems has increased, limitations of the information transmission speed capabilities of busses have become a significant problem, the conductive traces, or electrical conductors, laid on a backpanel acting as considerably less-than-perfect transmission lines. Consequently, the system speed performance ratings have been correspondingly limited by the bus "bottlenecks".
In addition, the line driver for each line of a bus provided in each transaction member has had to have sufficient current driving capability to drive all the line receivers in all the other transaction members at the desired rate. This fact has brought about the necessity to oversize the drivers which increases initial system cost, requires more power and also adversely affects the bus speed performance because of the capacitive reactances of the bus lines when carrying higher than necessary currents. The currents are theoretically higher than necessary because it is rarely necessary for a given transaction member to transmit information to more than one or two other transaction members at a given instant even though there may be many more transaction members organized around a given bus. The present invention is directed to minimizing the speed and cost consequences of these two related characteristics.